The present invention relates to integrated circuit packages, and more particularly to an integrated circuit chip carrier to be used in such packages to support one or more large scale integrated chips and to provide the metallization for interconnecting the supported chips and for connecting the supported chips to outside structures, e.g., supporting beds in a computer which may contain other integrated circuit packages.
As the integrated circuit technology advances in large scale integration towards denser integrated circuit chips containing in the order of thousands of circuits per chip, it is necessary to provide supporting electrical packaging or chip carriers structurally compatible with such chips and compatible with the performance demands of the circuitry in such chips.
At present, the circuit densities in advanced integrated circuit chips appear to have reached a point that the traditional ceramic chip carriers appear to have reached the limits of their structural compatability with respect to such advanced integrated circuit chips. The traditional ceramic modules or carriers employ what is known as a "thick film" paste technology in which silk screen and other mechanical techniques are used to apply the module or carrier metallurgy and insulative material. Such thick film metallurgy must have lateral dimensions and spacing at least one order of magnitude greater than the integrated circuit chip metallization and contact metallurgy which is produced by "thin film" techniques involving vapor deposition and photolithographic chemical and sputter etching.
One approach in the art for maintaining the structural compatibility between the advanced integrated circuit chips and the ceramic thick film modules is the use of multi-level thick film ceramic modules in which the thick film metallization is formed in a series of interconnected planes separated by insulative ceramic material. However, in order to structurally accommodate advanced integrated circuit chips containing thousands of circuits and metallurgy linework in the order of 0.3 mils, the multi-layer ceramic substrate which is limited to metallic lines in the order of 3 mils, must utilize, for example, more than 20 levels of metallurgy in order to form the necessary interconnection for a high circuit density chip having only two or three levels of metallurgy. Such multi-layered ceramic modules are expensive to produce and relatively large in size in an art whose direction is towards increased miniaturization. In addition, such multi-layer ceramic carriers impose structural limitations on the chip in order for the chip to be structurally compatible with the ceramic carrier. Where, for example, the chips are to be mounted on the ceramic carrier by solder reflow techniques such as those described in U.S. Pat. Nos. 3,495,133; 3,548,925 or 3,392,442, the solder reflow pads on the chip must be in the order of 4 mils in height and about 4 mils in width. Otherwise, the difference in coefficients of thermal expansion between the multi-layer ceramic module and the semiconductor, e.g., silicon, material in the chip would create sufficient stress on the pads to fracture the joints between chip and module. As a result, the chip pad must occupy many times the amount of valuable "real estate" or chip surface area than would be otherwise required if the pad could have dimensions in the order of 0.5 mils and be produced by the standard photolithographic thin film techniques.
In addition, because of the above-mentioned differences in coefficients of thermal expansion, it is undesirable to join by solder reflow chips having dimensions on a side greater than 200 mils to the ceramic substrate.
Because of these limitations in multi-layered ceramic modules for advanced integrated circuit chips with high circuit densities, consideration has been given to the concept of "computer on a wafer" wherein all of the circuitry necessary to perform the particular computer function including all internal interconnections would be formed on a single wafer. This would make the chip carriers with their interconnection functions unnecessary. The primary shortcoming of such an approach is that because of the complexity of such a wafer structure, yields are extremely low, and consequently, great numbers of integrated circuit wafers made at great expense have to be scrapped because of the likely incidence of a defect.
While there is some indication in the art of the use of carriers for integrated circuit chips made out of the same or similar semiconductor materials as the chips, such carriers appear not to have been previously applicable for supporting the advanced integrated circuit chips having thousands of circuits. This may be in large part due to the fact that even with the use of thin film technology permitted by such semiconductor material carriers, the carrier must still have more than four levels of metallurgy in order to provide the necessary interconnection for advanced chips of high circuit density. Unfortunately, until now, with metallurgies having line widths and spacing in the order of 0.3 mils, it was structurally not practical to form multi-level thin film metallurgy having more than three levels of metallization. In structures utilizing multi-layer metallurgy formed by conventional thin film techniques, there is deposited over each level metallization pattern, the passivating or insulating layer of dielectric material. This deposition is made by conventional chemical vapor deposition or sputter deposition techniques. A line in the metallization pattern will result in a corresponding elevation in the covering dielectric layer over the metallization pattern. Then, after a subsequent level metallization pattern is deposited onto the covering layer and it, in turn, covered by an additional dielectric layer, the upper surface of the additional covering layer will display the cumulative effects of both underlying metallization patterns. The surface will display a combination of three different heights: a lowermost height where there is no underlying metallization line, an intermediate height where there is only an underlying metallization line at one metallization level and the greatest height in portions of the surface where there are underlying lines from both levels of metallization patterns. As may be seen, with three levels of metallization, the uppermost covering dielectric layer will have even a greater variety of height combinations. As previously indicated, with metallization patterns having lines in the order of 0.3 mils, the effect of these irregularities in elevation becomes so pronounced that it is impractical to try and utilize more than three levels of metallization. We have, in such cases, a "sky-scraper" effect wherein the cumulative metal lines produce pronounced elevations which render the surface so irregular that the metal lines in the pattern extend over a very bumpy surface. This leads to discontinuities in the metal lines.
Because of these irregularities, in structures with more than three levels of metallization, the interconnection of subsequent levels to underlying levels by means of via holes becomes quite unpredictable and inconsistent. In addition, even in structures having three levels of metallization, it is not consistently possible to design a structure wherein a via hole through a given covering layer of dielectric material can be so positioned as to coincide with or overlap an underlying via hole through a lower dielectric layer.